This invention relates generally to the field of matrix-array, read-write, randomly accessible memory devices (RAMs), more particularly to the design of a memory cell for use in a multi-port static RAM memory, and especially to overcoming certain limitations on the speed with which such cells can be written with data.
In the quest to increase the speed of digital computers, the use of multiple data processors has become increasingly significant. Since microprocessors have vastly reduced the cost of computing power, distribution of the multiple computational tasks among multiple processing units has become practical.
However, the multiple processing units must in many instances share access to data stored in the memories of the computer. Since the read-write RAM memories of the computer will typically be accessed very frequently by more than one processing unit in such a multi-processor environment, adequate management of these memories to avoid contentions and errors becomes a vital concern.
The first multi-port static RAMs to appear are dual-port, although RAMs having three or more ports may very well appear in the future. The dual-port static RAM (SRAM) which has already evolved eases some of the management problems involved in the sharing of memory among multiple processors. In the dual-port SRAM, each of the memory cells may be accessed by either or both of two identical ports, conventionally called the left and right ports, each of which can access the cell for read and write operations. While the provision of two such ports eases the problem of contentions and avoids a requirement to provide a queued management scheme for access to the memory, certain problems still remain.
In particular, it has been noted that the operation of writing data into a memory cell proceeds more slowly when the row on which the cell is located is being accessed simultaneously by each of the two ports. Since the processing units accessing the memory may be operated asynchronously, the occurrence of this "common-row write problem" is not easily predicted. Consequently, additional time must be allowed for any write operation, and the speed of the memory device suffers.
As will appear from the discussions later in this patent application, the common-row write problem arises fundamentally from insufficient ability of the prior-art memory cell to raise the voltage on its bit-lines to a logic 1 level, compared to the speed with which this voltage can be dropped to a logic 0. This problem arises basically from the greater parasitic capacitance associated with the dual-port design.
While a number of alternatives exist for overcoming this problem, as by increasing the ability of the write drivers to deliver current, by increasing the size of the "pull-up" gates on the bit-lines, or by increasing the size (and hence decreasing the resistance) of the word-line pass gates, these solutions all involve degradation of some other performance criterion to an unacceptable degree. In particular, excessive increases in current consumption and power dissipation, or in the physical size and capacitance of each cell are often involved.